1. Field of the Invention
The present invention relates generally to a digital still camera and an image data processor. More particularly, the present invention relates to a digital still camera that compresses a video signal acquired by photographing an object with a CCD imaging device, stores it in a storage element, reads said compressed video signal from the storage element and reproduces said video signal. Further, the present invention particularly relates to an image data processor wherein time required for image data expansion processing is reduced by generating luminance data and color difference data having a first data length and generating therefrom a block of data to be written composed of luminance data and color difference data having second data length equivalent to the double of the first data length, supplying these data to be written to a frame memory in units of block and writing the block of data to the frame memory.
2. Description of the Related Art
A digital still camera writes image data output from a large scale integrated circuit (LSI) for expansion to a frame memory when image data (luminance data and color difference data) compressed and stored after imaging is reproduced.
FIG. 1 shows a configuration of an image data expansion processor 200 used in the conventional digital still camera. The processor 200 is composed of an expansion processing unit (LSI for expansion) 201 for performing data expansion processing on compressed image data Vcmp which is a reproduced data from a PC card and others, a buffer memory 202 for temporarily storing an image data Vout output from the expansion processing unit 201, a frame memory 204Y for storing a luminance data Y of the image data Vout, a frame memory 204C for storing a blue color difference data Cb and a red color difference data Cr of the image data Vout and a memory controller 203 for reading the image data Vout from the buffer memory 202 and sequentially writing it to the frame memories 204Y and 204C.
The expansion processing unit 201 outputs the luminance data Y, the blue color difference data Cb and the red color difference data Cr. They respectively have 8-bit data length and are sequentially output in units of block composed of xe2x80x9ceight pixelsxc3x978 linesxe2x80x9d as the image data Vout.
The luminance data Y, the blue color difference data Cb and the red color difference data Cr correspond to a video signal in xe2x80x9c4 to 2 to 2xe2x80x9d mode. In the case of the xe2x80x9c4 to 2 to 2xe2x80x9d mode, these color difference data Cb and Cr respectively include a half of the information of luminance data Y. That is, in the case of the xe2x80x9c4 to 2 to 2xe2x80x9d mode, these color difference data Cb and Cr are composed of xe2x80x9c4 pixelsxc3x978 linesxe2x80x9d shown in FIGS. 2B and 2C while the luminance data Y is composed of xe2x80x9c8 pixelsxc3x978 linesxe2x80x9d shown in FIG. 2A.
Therefore, the expansion processing unit 201 outputs two blocks of luminance data Y, one block of blue color difference data Cb and one block of red color difference data Cr repeatedly in the above order, as shown in FIG. 3A. In this case, the color difference data Cb and Cr are respectively composed of xe2x80x9c8 pixelsxc3x978 linesxe2x80x9d as one block. Therefore, they have an area corresponding to two blocks of luminance data Y. The respective pixel data b0, b2, b4, - - - , r0, r2, r4, - - - of the color difference data Cb and Cr shown in FIGS. 2B and 2C are data in the same position as the pixel data y0, y2, y4, - - - of the luminance data Y shown in FIG. 2A.
As described above, the luminance data Y, the color difference data Cb and Cr sequentially output from the expansion processing unit 201 as image data Vout are sequentially stored in the frame memories 204Y and 204C under the control of the memory controller 203 as shown in FIG. 3B after the above data is temporarily stored in the buffer memory 202.
If the luminance data Y is illustratively stored in the frame memory 204Y, an address (RAS address) in the direction of lines is switched every 8 pieces of pixel data as shown in FIG. 4 and pixel data is written as to 64 pieces of pixel data, y0 to y63 constituting the luminance data Y0, Y1, Y2, Y3, - - - of each block. Therefore, as shown in FIG. 3C, time, Tad, for switching an address is required every time 8 pieces of pixel data are written. As a result, time required for writing pixel data for one block in the frame memory 204Y is longer than the time required for outputting the pixel data y0 to y63 of one block from the expansion processing unit 201.
Also, if the color difference data Cb and Cr are illustratively stored in the frame memory 204C, an address (RAS address) in the direction of lines is switched every 8 pieces of pixel data as shown in FIG. 5 and pixel data are written as to 64 pieces of pixel data constituting the color difference data Cb0, Cr0, Cb2, Cr2, - - - of each block. In this case, the blue color difference data Cb0, Cb2, - - - are written to the even addresses of each line as xe2x80x9cb0, b2, b4, b6, b0, b2, b4, b6xe2x80x9d, xe2x80x9cb8, b10, b12, b14, b8, b10, b12, b14xe2x80x9d, - - - and the red color difference data Cr0, Cr2, - - - are written to the odd addresses of each line as xe2x80x9cr0, r2, r4, r6, r0, r2, r4, r6xe2x80x9d, xe2x80x9cr8, r10, r12, r14, r8, 10, r12, r14xe2x80x9d, - - - .
As described above, if the color difference data Cb and Cr are stored in the frame memory 204C, the time, Tad, for switching an address is also required every time 8 pieces of pixel data are written. As a result, time required for writing one block of pixel data to the frame memory 204C is longer than time required for outputting one block of pixel data from the expansion processing unit 201.
In the conventional digital still camera, to adjust difference between time required for writing the above one block of pixel data to the frame memories 204Y and 204C and time required for outputting one block of pixel data from the expansion processing unit 201, the processing of the expansion processing unit 201 stops every time the image data Vout of one block is output (see a period Tst in which expansion processing is stopped shown in FIG. 3A) and, at the next block, the pixel data is written to the frame memories 204Y and 204C at the same timing as the output timing of the expansion processing unit 201 has been executed.
Similarly, in the conventional image data processor 200, writing image data, Vout, to the frame memories 204Y and 204C takes much time and to adjust time, a measure of stopping the processing of the expansion processing unit 201 has been taken. Therefore, there has been a problem that it takes relatively much time to execute processing for expanding image data.
The object of the present invention is to provide a digital still camera and an image data processor wherein time required for expanding image data is reduced.
In carrying out the present invention as one preferred embodiment, I provide a digital still camera that compresses a video signal acquired by photographing an object with a CCD imaging device, stores it in a storage element, reads said compressed video signal from the storage element and reproduces said video signal. The digital still camera comprises expansion processing means for performing expansion processing on said compressed video signal and outputting the video signal in units of block as luminance data and color difference data respectively having a first data length, a frame memory having a second data length equivalent to the double of the first data length, video data block generating means for generating a block of video data having the second data length by connecting the luminance data and the color difference data respectively having the first data length and output from the expansion processing means in units of block, and writing means for writing a signal output from the video data block generating means to the frame memory in units of block of said video data.
Further, as another preferred embodiment, I provide an image data processor comprising an expansion processing means for expanding a compressed video signal as luminance data and color difference data respectively having a first data length and sequentially outputting the expanded video data in units of block, a frame memory having a second data length equivalent to the double of the first data length and data writing means for generating a block of data to be written having the second data length and writing the data to be written to the frame memory in units of block, the data to be written comprising the luminance data and the color difference data respectively having the first data length and output from the expansion processing means.
According to the present invention, compressed image data (for example, image data compressed according to Joint Photographic Experts Group (JPEG) method) is expanded in the expansion processing means. The luminance data and the color difference data respectively having first data length (for example, 8-bit data length) are sequentially output in units of block from the expansion processing means. Then, a block of data to be written having second data length (for example, 16-bit data length) is generated from the luminance data and the color difference data. For example, 8-bit luminance data is allocated on the side of high order bits and 8-bit color difference data is allocated on the side of low order bits so that a block of 16-bit data to be written is generated.
The data to be written generated as described above having second data length is written to the frame memory having second data length in units of block. In this case, when a block is composed of xe2x80x9c8 pixelsxc3x978 linesxe2x80x9d, an address in the direction of lines is switched every 8 pieces of pixel data and the data is written.
Therefore, time for switching an address is required and then time for stopping the processing of the expansion processing means is required to adjust time. However, in the present invention, each of luminance data and color difference data respectively having first data length is not written in the frame memory in units of block but data to be written having second data length and composed of the luminance data and the color difference data is written to the frame memory in units of block.
Therefore, as the number of blocks written to the frame memory decreases, total time required for switching an address also decreases. Hereby, a period that the processing of the expansion processing means stops to adjust time can be also reduced and time required for expanding image data can be reduced.
A further understanding of the nature and advantages of the invention may be realized by reference to the following portions of the specification and drawings.